IDT72V73273_07 Datasheet, PDF (1/36 Pages) Integrated Device Technology – 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS

3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE
MATCHING 32,768 X 32,768 CHANNELS
IDT72V73273
FEATURES:
• Up to 64 serial input and output streams
• Maximum 32,768 x 32,768 channel non-blocking switching
• Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,
16.384Mb/s or 32.768Mb/s
• Rate matching capability: rate selectable on both RX and TX
in eight groups of 8 streams
• Optional Output Enable Indication Pins for external driver
High-Z control
• Per-channel Variable Delay Mode for low-latency applications
• Per-channel Constant Delay Mode for frame integrity applications
• Enhanced Block programming capabilities
• TX/RX Internal Bypass
• Automatic identification of ST-BUS^ and GCI serial streams
• Per-stream frame delay offset programming
• Per-channel High-Impedance output control
• Per-channel processor mode to allow microprocessor writes to TX
streams
• Bit Error Rate Testing (BERT) for testing
• Direct microprocessor access to all internal memories
• Selectable Synchronous and Asynchronous microprocessor
bus timing modes
• IEEE-1149.1 (JTAG) Test Port
• 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA)
• Operating Temperature Range -40°C to +85°C
DESCRIPTION:
The IDT72V73273 has a non-blocking switch capacity of 32,768 x 32,768
channels at 32.768Mb/s. With 64 inputs and 64 outputs, programmable per
stream control, and a variety of operating modes the IDT72V73273 is
designed for the TDM time slot interchange function in either voice or data
applications.
Some of the main features of the IDT72V73273 are LOW power 3.3 Volt
operation, automatic ST-BUS^® /GCI sensing, memory block programming,
simple microprocessor interface , JTAG Test Access Port (TAP) and per
stream programmable input offset delay, variable or constant throughput
modes, output enable and processor mode, BER testing, bypass mode, and
advanced block programming.
FUNCTIONAL BLOCK DIAGRAM
RX0-7
RX8-15
RX16-23
RX24-31
RX32-39
RX40-47
RX48-55
RX56-63
Receive
Serial Data
Streams
Timing Unit
VCC
GND
RESET
ODE
Data Memory
MUX
Internal
Registers
Connection
Memory
Microprocessor Interface
Transmit
Serial Data
Streams
JTAG Port
TX0-TX7
TX8-15/OEI0-7
TX16-23
TX24-31/OEI16-23
TX32-39
TX40-47/OEI32-39
TX48-55
TX56-63/OEI48-55
C32i F32i
S/A D S C S R/W A0-A15 BEL D TA/ _D0-D15
BEH
TMS TDI TCKTDO TR ST
6140 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS^ is a trademark of Mitel Corp.
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 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
February 9, 2009
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