IDT70V7319S Datasheet, PDF (6/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V7319S
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control^(1,2,3,4)
OE³ CLK CE0 CE1 UB
Upper Byte Lower Byte
LB R/W
I/O9-17
I/O0-8
MODE
X
↑
H
X
X
X
X
High-Z
High-Z Deselected–Power Down
X
↑
X
L
X
X
X
High-Z
High-Z Deselected–Power Down
X
↑
L
H
H
H
X
High-Z
High-Z All Bytes Deselected
X
↑
L
H
H
L
L
High-Z
DIN
Write to Lower Byte Only
X
↑
L
H
L
H
L
DIN
High-Z Write to Upper Byte Only
X
↑
L
H
L
L
L
DIN
DIN
Write to both Bytes
L
↑
L
H
H
L
H
High-Z
DOUT Read Lower Byte Only
L
↑
L
H
L
H
H
DOUT
High-Z Read UpperByte Only
L
↑
L
H
L
L
H
DOUT
DOUT Read both Bytes
H
X
X
X
X
X
X
High-Z
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5629 tbl 02
Truth Table II—Address and Address Counter Control^(1,2,7)
Previous Addr
Address Address Used CLK ADS CNTEN REPEAT⁽⁶⁾ I/O⁽³⁾
MODE
An
X
An
↑
L⁽⁴⁾
X
H
DI/O (n) External Address Used
X
An
An + 1 ↑
H
L⁽⁵⁾
H
DI/O(n+1) Counter Enabled—Internal Address generation
X
An + 1 An + 1 ↑
H
H
H
DI/O(n+1) External Addre ss Blocked—Counter disab led (An + 1 reused)
X
X
An
↑
X
X
L⁽⁴⁾
DI/O(0) Counter Set to last valid ADS load
NOTES:
5629 tbl 03
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB/LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB/LB
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB/LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L
- BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.
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