IDT70V7319S Datasheet, PDF (1/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 3.3V 256K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7319S
Features:
◆ _{256K x 18 Synchronous Bank-Switchable Dual-ported}
SRAM Architecture
– 64 independent 4K x 18 banks
– 4 megabits of memory on chip
◆ _{Bank access controlled via bank address pins}
◆ _{High-speed data access}
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{LVTTL- compatible, 3.3V (±150mV) power supply}
for core
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 166MHz and 133MHz
◆ _{Available in a 144-pin Thin Quad Flatpack (TQFP),}
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
◆ _{Supports JTAG features compliant with IEEE 1149.1}
– Due to limited pin count, JTAG is not supported on the
144-pin TQFP package.
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
UBL
LBL
OEL
CONTROL
LOGIC
MUX
4Kx18
MEMORY
ARRAY
(BANK 0)
CONTROL
LOGIC
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O0L-17L
I/O
CONTROL
A11L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
©2002 Integrated Device Technology, Inc.
MUX
MUX
4Kx18
MEMORY
ARRAY
(BANK 1)
MUX
TDI
TDO
MUX
4Kx18
MEMORY
ARRAY
(BANK 63)
MUX
JTAG
TMS
TCK
TRST
1
I/O
CONTROL
I/O0R-17R
ADDRESS
DECODE
BANK
DECODE
A11R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
,
5629 drw 01
DECEMBER 2002
DSC 5629/6