IDT70V18L Datasheet, PDF (6/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 9 DUAL-PORT STATIC RAM

IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
4854 tbl 11
Preliminary
Industrial and Commercial Temperature Ranges
3.3V
3.3V
DATAOUT
BUSY
INT
435Ω
590Ω
30pF
DATAOUT
435Ω
590Ω
5pF*
4854 drw 03
4854 drw 04
Figure 1. AC Output Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Waveform of Read Cycles⁽⁵⁾
ADDR
CE⁽⁶⁾
OE
R/W
DATAOUT
(4)
tAA
tACE⁽⁴⁾
tAOE⁽⁴⁾
tLZ ⁽¹⁾
BUSYOUT
tRC
VALID DATA⁽⁴⁾
tOH
tHZ⁽²⁾
(3,4)
tBDD
4854 drw 05
Timing of Power-Up Power-Down
CE⁽⁶⁾
tPU
ICC
50%
ISB
tPD
50%
.
4854 drw 06
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer toTruth Table I - Chip Enable.
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