IDT70V18L Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 9 DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
64K x 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V18L
.eatures
x _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
x _{High-speed access}
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
x _{Low-power operation}
– IDT70V18L
Active: 440mW (typ.)
Standby: 660µW (typ.)
x _{Dual chip enables allow for depth expansion without}
external logic
x _{IDT70V18 easily expands data bus width to 18 bits or}
more using the Master/Slave select when cascading more
than one device
x _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
x _{Busy and Interrupt Flags}
x _{On-chip port arbitration logic}
x _{Full on-chip hardware support of semaphore signaling}
between ports
x _{Fully asynchronous operation from either port}
x _{LVTTL-compatible, single 3.3V (±0.3V) power supply}
x _{Available in a 100-pin TQFP}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
.unctional Block Diagram
R/W L
CE0L
CE1L
OE_L
R/W_R
CE0R
CE1R
OE R
I/O 0-8L
I/O
Control
I/O
Control
BUSY
(1,2)
L
A15L
A0L
Address
Decoder
16
CE _0L
CE1L
OE L
R/W L
64Kx9
MEMORY
ARRAY
70V18
16
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
INT
(2)
L
(1)
M/S
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2002 Integrated Device Technology, Inc.
Address
Decoder
I/O 0-8R
BUSY
(1,2)
R
A15R
A 0R
CE0R
CE1R
OER
R/WR
4854 drw 01
SEMR
INT R⁽²⁾
JANUARY 2002
DSC-4854/3