ICS9FG108D Datasheet, PDF (6/18 Pages) Integrated Device Technology – Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = Tambient, Supply Voltage V_DD = 3.3 V +/-5%
SPEC
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
V_SS - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull- _-5
up resistors
I_IL2
V_IN = 0 V; Inputs with pull-up _-200
resistors
V_DD + 0.3 _V
1
0.8
V
1
5
uA
1
uA
1
uA
1
Operating Supply Current
(T_A = Commercial)
DIF_STOP# Current
(T_A = Commercial)
Operating Supply Current
(T_A = Industrial)
IDD_VDD
IDD_VDDA
IDD_VDD
IDD_VDDA
IDD_VDDPD
IDD_VDDAPD
IDD_VDDPD
IDD_VDDAPD
IDD_VDD
IDD_VDD
IDD_VDDA
IDD_VDDA
DIF_STOP# Current
(T_A = Industrial)
IDD_VDDPD
IDD_VDDAPD
Input Frequency³
Pin Inductance¹
Input/Output
Capacitance¹
Clk Stabilization^1,2
Spread Modulation
Frequency
Spread Modulation %
Spread Modulation %
DIF output enable
F_i
L_pin
C_IN
C_OUT
T_STABcom
T_STABind
f_MOD
f_MOD%DWN
f_MOD%CTR
t_DIFOE
C_L=Full load; fout = 400 MHz
C_L=Full load; fout = 100 MHz
All DIF pairs stopped in driven
mode
All DIF pairs stopped in Hi-Z
mode
C_L=Full load; fout = 400 MHz
C_L=Full load; fout = 100 MHz
All DIF pairs stopped in driven
mode
All DIF pairs stopped in Hi-Z
mode
SEL14M_25M# = 0
SEL14M_25M# = 1
Logic Inputs
Output pin capacitance
From V_DD Power-Up to 1st
clock
From V_DD Power-Up to 1st
clock
SEL14M_25M# = 0
SEL14M_25M# = 1
Down Spread Selected
Center Spread Selected
DIF output enable after
DIF_Stop# de-assertion
186
22
156
22
148
22
30
22
205
24
172
24
163
24
33
24
22.50 25.00
12.89 14.31818
1.5
215
25
179
25
170
25
35
25
236
28
198
28
187
28
38
28
28.00
15.75
7
5
6
1.8
3
32.541
32.467
-0.5
+/-0.25
15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MHz
MHz
nH
pF
pF
ms
ms
kHz
kHz
%
%
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
1
1
1
1,2
1,2
1,3,4
1,3,4
1,3,4
1,3,4
1
Input Rise and Fall times t_R/t_F
20% to 80% of VDD
5
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REF pin and tuned to 0 PPM to meet}
ppm frequency accuracy on PLL outputs.
4 _{These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency will scale}
these frequencies accordingly. The output frequecy selected by the FS inputs will also scale. For example, 27MHz
input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 = 108MHz.
IDT^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1542E 12/16/10
6