ICS853S024 Datasheet, PDF (6/16 Pages) Integrated Device Technology – LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

ICS853S024
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
Parameter Measurement Information, continued
nQ0:nQ21
Q0:Q21
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Output Duty Cycle/Pulse Width/Period
Clock
20%
Outputs
80%
t_R
Output Rise/Fall Time
PRELIMINARY
80%
t_F
V_{SW I N G}
20%
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V_CC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Single Ended Clock Input
V_REF
C1
0.1u
V_CC
R1
1K
CLK
nCLK
R2
1K
LOW SKEW LVPECL FANOUT BUFFER
Figure 1. Single-Ended Signal Driving Differential Input
6
ICS853S024AY REV. A APRIL 30, 2008