9ZML1232 Datasheet, PDF (6/19 Pages) Integrated Device Technology – 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI

9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = T_COM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
T_COM
Commmercial range
0
25
70
°C
1
V_IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2
V_DD + 0.3 V
1
V_IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND - 0.3
0.8
V
1
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
-0.12
5
uA
1
Input Current
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
-0.02
200
uA
1
V_IN = VDD; Inputs with internal pull-down resistors
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
F_ibyp
F_ipll
L_pin
C_IN
C_{INDIF_IN}
V_DD = 3.3 V, Bypass mode
V_DD = 3.3 V, 100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
33
150
MHz
2
90
100.00 110
MHz
2
7
nH
1
1.5
5
pF
1
1.5
2.7
pF
1,4
C_OUT
Output pin capacitance
6
pF
1
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1
ms
1,2
Input SS Modulation
Allowable Frequency
Frequency
f_MODIN
(Triangular Modulation)
30
33
kHz
1
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
t_F
Fall time of control inputs
Trise
t_R
Rise time of control inputs
SMBus Input Low Voltage V_ILSMB
SMBus Input High Voltage V_IHSMB
2.1
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
SMBus Sink Current
I_PULLUP
@ V_OL
4
Nominal Bus Voltage
V_DDSMB
3V to 5V +/- 10%
2.7
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
t_FSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating
Frequency
f_MAXSMB
Maximum SMBus operating frequency
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4_{DIF_IN input}
5_{The differential input clock must be running for the SMBus to be active}
12 clocks 1
300
us
1,3
5
ns
1,2
5
ns
1,2
0.8
V
1
V_DDSMB
V
1
0.4
V
1
mA
1
5.5
V
1
1000
ns
1
300
ns
1
400
kHz 1,5
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
6
9ZML1232
REV E 112015