9FGU0241 Datasheet, PDF (6/15 Pages) Integrated Device Technology – Programmable output amplitude

9FGU0241 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDxx
Supply voltage for core, analog and single-ended
LVCMOS outputs
1.425
1.5
1.575
V
Ambient Operating
Temperature
T_AMB
Comercial range
Industrial range
0
25
70
°C
-40
25
85
°C
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
V_IH
Single-ended inputs, except SMBus
0.75 V_DD
V_DD + 0.3 V
V_IM
Single-ended tri-level inputs ('_tri' suffix)
0.4 V_DD 0.5 V_DD 0.6 V_DD
V
V_IL
Single-ended inputs, except SMBus
-0.3
0.25 V_DD V
V_IH
Single-ended outputs, except SMBus. I_OH = -2mA V_DD-0.45
V
V_IL
Single-ended outputs, except SMBus. I_OL = -2mA
0.45
V
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
Single-ended inputs
5
uA
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
200
uA
V_IN = VDD; Inputs with internal pull-down resistors
F_in
XTAL, or X1 input
23
25
27
MHz
L_pin
7
nH
1
C_IN
Logic Inputs, except DIF_IN
1.5
5
pF
1
C_OUT
Output pin capacitance
6
pF
1
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8
ms
1,2
SS Modulation Frequency
OE# Latency
f_MOD
t_LATOE#
Triangular Modulation
DIF start after OE# assertion
DIF stop after OE# deassertion
30
31.6
33
kHz
1
1
3
clocks 1,3
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_F
t_R
V_ILSMB
V_IHSMB
V_OLSMB
I_PULLUP
V_DDSMB
t_RSMB
t_FSMB
f_MAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
@ I_PULLUP
@ V_OL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
2.1
4
1.425
5
ns
2
5
ns
2
0.6
V
3.3
V
4
0.4
V
mA
3.3
V
1000
ns
1
300
ns
1
400
kHz
1
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Control input must be monotonic from 20% to 80% of input swing.}
3 _{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB}
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
6
REVISION A 09/24/14