9FGU0241 Datasheet, PDF (10/15 Pages) Integrated Device Technology – Programmable output amplitude

9FGU0241 DATASHEET
SMBus Table: Output Enable Register
Byte 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DIF OE1
DIF OE0
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Output Enable
Output Enable
Reserved
Type
RW
RW
0
Low/Low
Low/Low
1
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Name
Control Function
Bit 7
Bit 6
SSENRB1
SSENRB1
SS Enable Readback Bit1
SS Enable Readback Bit0
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
Bit 4
SSENSW1
SS Enable Software Ctl Bit1
Bit 3
SSENSW0
SS Enable Software Ctl Bit0
Bit 2
Reserved
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
Type
0
1
R 00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
RW
SS control locked
Values in B1[4:3]
control SS amount.
RW¹
RW¹
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW
00 = 0.55V
RW
10= 0.7V
01 = 0.65V
11 = 0.8V
Default
Latch
Latch
0
0
0
1
1
0
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Reserved
Reserved
Reserved
Reserved
Reserved
Adjust Slew Rate of DIF1
Adjust Slew Rate of DIF0
Reserved
Type
RW
RW
0
Slow Setting
Slow Setting
1
Fast Setting
Fast Setting
Default
1
1
1
1
1
1
1
1
SMBus Table: REF Control Register
Byte 3
Name
Bit 7
Bit 6
REF
Bit 5 REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Control Function
Slew Rate Control
Wake-on-Lan Enable for REF
REF Output Enable
Reserved
Reserved
Reserved
Reserved
Type
0
1
RW
00 = Slowest
01 = Slow
RW
10 = Fast
11 = Faster
RW
REF does not run in REF runs in Power
Power Down
Down
RW
Low
Enabled
Default
0
1
0
1
1
1
1
1
Byte 4 is reserved and reads back 'hFF'.
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
10
REVISION A 09/24/14