97U877AHLF Datasheet, PDF (6/13 Pages) Integrated Device Technology – 1.8V Wide Range Frequency Clock Driver

ICS97U8 7 7
Timing Requirements
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
Max clock frequency
freq_op
1.8V+0.1V @ 25°C
95
370
Application Frequency Range
freq_App
1.8V+0.1V @ 25°C
160
350
Input clock duty cycle
d_tin
40
60
CLK stabilization
T_STAB
15
UNITS
MHz
MHz
%
µs
Switching Characteristics¹
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
Output enable time
Output disable time
Period jitter
Half-period jitter
Input slew rate
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Static Phase Offset
Output to Output Skew
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
t_en
t_dis
t_{jit (per)}
t_jit(hper)
SLr1(i)
SLr1(o)
t_jit(cc+)
t_jit(cc-)
t_{( )dyn}
t_SPO2
t_skew
OE to any output
OE to any output
Input Clock
Output Enable (OE), (OS)
-30
-60
1
0.5
1.5
0
0
-20
-50
30.00
0.00
2.0
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
TYP MAX UNITS
4.73
8
ns
5.82
8
ns
30
ps
60
ps
2.5
4
v/ns
v/ns
2.5
3
v/ns
40
ps
-40
ps
20
ps
0
50
ps
40
ps
33 kHz
-0.50 %
MHz
0792A—04/15/04
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