8V79S680 Datasheet, PDF (6/52 Pages) Integrated Device Technology – JESD204B Compliant Fanout Buffer and Divider

8V79S680 Datasheet
Principles of Operation
Overview
The 8V79S680 is a JESD204B Fanout Buffer with Configurable Phase Delay. The device supports the division, phase-delay and distribution of
high-frequency clocks (input: CLK, nCLK) and the fanout and phase-delay of low-frequency synchronization (SYSREF) signals (input: REF/nREF).
Clock and SYSREF signal paths are independent and are organized in channels, with each channel consisting of several clock and SYSREF outputs.
Outputs are configurable with support for LVPECL, LVDS and four amplitude settings. Individual channels and unused circuit blocks support a
powered-down state for reduced power consumption operation. The register map, accessible through a SPI interface with read-back capability
controls the main device settings.
Signal Flow
The device offers four channels with the names A, B, C and D. Each channel supports individual frequency-division, phase-delay and fan-out functions
of the input clock to a total of eight QCLK_y clock outputs; each channel also distributes the SYSREF input signal to multiple QREF_r outputs with
individual per-output phase delay capability.
The central clock distribution ensures low skew clock outputs within each channel; outputs are synchronous across channels (independent on the
divider setting) on the incident rising clock edge for all outputs with equal phase delay settings.
SYSREF output are synchronous with each other for equal phase-delay settings. QCLK_y and QREF_r outputs will be phase-locked to each other if
the CLK and REF inputs are phase-locked. The phase-delay capability in each signal path can be used to establish repeatable and deterministic clock
to SYSREF phase relationships at the outputs.
The CLK and QREF signal paths are optimized for channel isolation. allowing high-speed clocks of 983.04MHz, 1474.56MHz or 1966.08MHz (up to
3GHz) and lower-speed SYSREF signals at e.g. 7.68MHz or 9.6MHz with a minimum of signal crosstalk and spurious signals.
Clock Channel Divider
Each of the four independent frequency dividers N_A-N_D can be individually set to the divider values ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16. The dividers are
synchronous and have an equal propagation delay on the incident edge. See Table 2 for the supported frequency divider settings.
Table 2: N_A-D Frequency Divider Settings
N_A-D
Clock Divider
000
÷1
Divider bypass and powered down
001
÷2
010
÷4
011
÷6
100
÷8
101
÷12
110
÷16
111
Not defined
©2016 Integrated Device Technology, Inc
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August 4, 2016