8V79S680 Datasheet, PDF (19/52 Pages) Integrated Device Technology – JESD204B Compliant Fanout Buffer and Divider

8V79S680 Datasheet
Channel and Clock Output Registers
The content of the channel register and clock output registers set the clock divider, output style, amplitude, power down state, enable state and the
clock phase delay.
Table 13: Channel and Clock Output Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
0x20
0x30
0x40
Reserved Reserved Reserved Reserved Reserved
0x50
N_A[2:0]
N_B[2:0]
N_C[2:0]
N_D[2:0]
0x21
CLK_A[7:0]
0x31
CLK_B[7:0]
0x41
CLK_C[7:0]
0x51
CLK_D[7:0]
0x22
PD_A
0x32
0x42
PD_B
PD_C
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0x52
PD_D
0x24: QCLK_A0
0x25: QCLK_A1
0x26: QCLK_A2
PD_A0
PD_A1
PD_A2
Reserved
Reserved
STYLE_A0
STYLE_A1
STYLE_A2
A_A0[1:0]
A_A1[1:0]
A_A2[1:0]
Reserved
0x34: QCLK_B0
0x35: QCLK_B1
PD_B0
PD_B1
Reserved
Reserved
STYLE_B0
STYLE_B1
A_B0[1:0]
A_B1[1:0]
Reserved
0x44: QCLK_C0
0x45: QCLK_C1
PD_C0
PD_C1
Reserved
Reserved
STYLE_C0
STYLE_C1
A_C0[1:0]
A_C1[1:0]
Reserved
0x54: QCLK_D
PD_D
Reserved Reserved STYLE_D
A_D[1:0]
Reserved
0x74
EN_QCLK_A0 EN_QCLK_A1 EN_QCLK_A2 EN_QCLK_B0 EN_QCLK_B1 EN_QCLK_C0 EN_QCLK_C1 EN_QCLK_D
©2016 Integrated Device Technology, Inc
19
August 4, 2016