8T73S208_16 Datasheet, PDF (6/22 Pages) Integrated Device Technology – 2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer

8T73S208 Datasheet
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V_CC = V_CCO = 2.5V ± 5% or 3.3V ± 5%, T_A = -40°C to 85°C
Symbol¹ Parameter
Test Conditions
Minimum
Typical
f_REF
Input Frequency
IN, nIN
FSEL[1:0] = 00
f_OUT
Output Frequency
FSEL[1:0] = 01
FSEL[1:0] = 10
FSEL[1:0] = 11
f_SCL
I²C Clock Frequency
Buffer Additive Phase Jitter,
f_REF = 100MHz,
Integration Range: 12kHz – 20MHz
t_JIT
RMS; refer to Additive Phase
Jitter Section, measured with
f_REF = 125MHz,
Integration Range: 12kHz – 20MHz
FSEL[1:0] = 00
f_REF =156.25MHz,
Integration Range: 12kHz – 20MHz
0.293
0.219
0.182
FSEL[1:0] = 00
550
t_PD
Propagation
Delay²
IN, nIN to
Qx, nQx
FSEL[1:0] = 01
FSEL[1:0] = 10
675
815
FSEL[1:0] = 11
930
tsk(o)
Output Skew^{3 4}
15
tsk(p)
Pulse Skew
10
tsk(pp) Part-to-Part Skew^{3 5 6}
Any Frequency
50
odc
Output Duty Cycle⁷
at f_REF = 100MHz
at f_REF = 125MHz
48
50
48
50
at f_REF = 156.25MHz
48
50
t_PDZ
Output Enable and Disable
Time⁸
Output Enable/Disable State from/to
Active/Inactive
1
20% to 80%
140
t_R / t_F
Output Rise/ Fall Time
10% to 90%
180
Maximum
1000
1000
500
250
125
400
0.338
0.245
0.207
750
870
1052
1230
60
50
500
52
52
52
205
350
Units
MHz
MHz
MHz
MHz
MHz
kHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
%
%
µs
ps
ps
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. Measured from the differential input crossing point to the differential output cross point.
NOTE 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross point.
NOTE 4. This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 6. Part-to-part skew specification does not guarantee divider synchronization between devices.
NOTE 7. If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.
NOTE 8. Measured from SDA rising edge of I²C stop command.
©2016 Integrated Device Technology, Inc.
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Revision D, June 15, 2016