8T73S208_16 Datasheet, PDF (1/22 Pages) Integrated Device Technology – 2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer

2.5 V, 3.3 V Differential LVPECL
Clock Divider and Fanout Buffer
8T73S208
Datasheet
General Description
The 8T73S208 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
The integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I²C register. On power-up, all outputs are
enabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVPECL outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1000MHz
• LVCMOS interface levels for the control inputs
• Individual output enable/disabled by I²C interface
• Output skew: 15ps (typical)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 0.182ps (typical)
• Full 2.5V and 3.3V supply voltages
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
IN
nIN
50
f_REF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0]
Pulldown (2)
2
SDA ^Pullup
I²C
SCL ^Pullup
8
ADR[1:0] ^{Pulldown (2)}
2
Q0
nQ0
Q1
nQ1
FSEL1
24 23 22 21 20 19 18 17
25
16
nQ5
Q2
nQ2
Q3
nQ3
Q4
nQ4
IN ²⁶
V_T ²⁷
nIN ²⁸
V_CC ²⁹
SDA 30
SCL 31
Q5
nQ5
ADR0 32
8T73S208
15 Q5
14 _nQ4
13 _Q4
12 _nQ3
11 Q3
10 nQ2
9 Q2
Q6
nQ6
12345678
Q7
nQ7
32-pin, 5mm x 5mm VFQFN
©2016 Integrated Device Technology, Inc.
1
Revision D, June 15, 2016