89HPES6T6G2 Datasheet, PDF(6/30 Page) Integrated Device Technology – Low latency cut-through switch architecture

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89HPES6T6G2 Datasheet, PDF (6/30 Pages) Integrated Device Technology – Low latency cut-through switch architecture

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IDT 89HPES6T6G2 Data Sheet

Signal

JTAG_TRST_N

Type

Name/Description

I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is rec-

ommended to meet the JTAG specification in cases where the tester can

access this signal. However, for systems running in functional mode, one of

the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 5 Test Pins (Part 2 of 2)

Signal

REFRES0

REFRES1

REFRES2

REFRES3

REFRES4

REFRES5

VDDCORE

VDDI/O

VDDPEA

VDDPEHA

VDDPETA

VSS

Type

Name/Description

I/O Port 0 External Reference Resistor. Provides a reference for the Port 0

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor

should be connected from this pin to ground.

I/O Port 1 External Reference Resistor. Provides a reference for the Port 1

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor

should be connected from this pin to ground.

I/O Port 2 External Reference Resistor. Provides a reference for the Port 2

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor

should be connected from this pin to ground.

I/O Port 3 External Reference Resistor. Provides a reference for the Port 3

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor

should be connected from this pin to ground.

I/O Port 4 External Reference Resistor. Provides a reference for the Port 4

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor

should be connected from this pin to ground.

I/O Port 5 External Reference Resistor. Provides a reference for the Port 5

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor

should be connected from this pin to ground.

I Core VDD. Power supply for core logic.

I I/O VDD. LVTTL I/O buffer power supply.

I PCI Express Analog Power. Serdes analog power supply (1.0V).

I PCI Express Analog High Power. Serdes analog power supply (2.5V).

I PCI Express Transmitter Analog Voltage. Serdes transmitter analog

power supply (1.0V).

I Ground.

Table 6 Power, Ground, and SerDes Resistor Pins

6 of 30

March 30, 2011

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