89HPES6T6G2 Datasheet, PDF (1/30 Pages) Integrated Device Technology – Low latency cut-through switch architecture

6-Lane 6-Port
Gen2 PCI Express® Switch
®
89HPES6T6G2
Data Sheet
Device Overview
The 89HPES6T6G2, a 6-lane 6-port Gen2 PCI Express® switch, is a
member of IDT’s PRECISE™ family of PCI Express switching solutions.
The PES6T6G2 is a peripheral chip that performs PCI Express Base
switching with a feature set optimized for servers, storage, communica-
tions, and consumer applications. It provides connectivity and switching
functions between a PCI Express upstream port and five downstream
ports or peer-to-peer switching between downstream ports.
Features
◆ _{High Performance PCI Express Switch}
– Six Gen2 PCI Express lanes supporting 5 Gbps and
2.5 Gbps operation
• One x1 upstream port
• Five x1 downstream ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2Kbytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Supports in-band hot-plug presence detect capability
– Supports external signal for hot plug event notification allowing
SCI/SMI generation for legacy operating systems
Block Diagram
– Configurable downstream port PCI-to-PCI bridge device
numbering
– Crosslink support
– Supports ARI forwarding defined in the Alternative Routing-ID
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
– Ability to load device configuration from serial EEPROM
◆ _{Legacy Support}
– PCI compatible INTx emulation
– Supports bus locked transactions, allowing use of PCI Express
with legacy software
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates six 5 Gbps / 2.5 Gbps embedded SerDes, 8B/10B
encoder/decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Ability to disable peer-to-peer communications
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
protected
– Supports PCI Express hot-plug on all downstream ports
– Supports upstream port hot-plug
– Hot-swap capable I/O
– External Serial EEPROM contents are checksum protected
Frame Buffer
6-Port Switch Core / 6 Gen2 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
(Port 0)
(Port 1)
Figure 1 Internal Block Diagram
© 2011 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 30
(Port 5)
March 30, 2011
DSC 6930