82P33831_16 Datasheet, PDF (6/13 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and 10G/40G Synchronous Ethernet

82P33831 Short Form Datasheet
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PIN DESCRIPTION
Table 1: Pin Description
Pin No.
E1
K8
A11
K6
H1
J1
J2
K10
K9
M12
M11
L12
L11
K12
K11
J12
J11
G12
G11
Name
OSCI
MS/SL
SONET/SDH/
LOS3
RSTB
XO_FREQ0/
LOS0
XO_FREQ1/
LOS1
XO_FREQ2/
LOS2
IN1
IN2
IN3_POS
IN3_NEG
IN4_POS
IN4_NEG
IN5_POS
IN5_NEG
IN6_POS
IN6_NEG
IN7_POS
IN7_NEG
I/O
Type
Description
Global Control Signal
OSCI: Crystal Oscillator System Clock
I
CMOS A clock provided by a crystal oscillator is input on this pin. It is the system clock for the
device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2.
I
pull-up
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the
Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit.
I
pull-down
I
pull-up
CMOS
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, this pin takes on the operation of LOS3.
LOS3- This pin is used to disqualify input clocks.
RSTB: Reset
I
pull-down
CMOS
XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.
XO_FREQ[2:0] Oscillator Frequency (MHz)
000
10.000
001
12.800
010
13.000
011
19.440
100
20.000
101
24.576
110
25.000
111
30.720
LOS0 ~ LOS2 - These pins are used to disqualify input clocks. After reset, these pins take on
the operation of LOS0-2.
Input Clock and Frame Synchronization Input Signal
IN1: Input Clock 1
I
AMI
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
AMI input has internal 1k ohm to 1.5V termination. This pin can also be used as a frame
pulse input, and in this case an 8 kHz signal can be input on this pin.
IN2: Input Clock 2
I
AMI
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
AMI input has internal 1k ohm to 1.5V termination. This pin can also be used as a frame
pulse input, and in this case an 8 kHz signal can be input on this pin.
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
I
PECL/LVDS A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
I
PECL/LVDS A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
I
PECL/LVDS A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN6_POS / IN6_NEG: Positive / Negative Input Clock 6
I
PECL/LVDS A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN7_POS / IN7_NEG: Positive / Negative Input Clock 7
I
PECL/LVDS A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
©2016 Integrated Device Technology, Inc.
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Revision 6, March 24, 2016