82P33831_16 Datasheet, PDF (3/13 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and 10G/40G Synchronous Ethernet

82P33831 Short Form Datasheet
In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, DPLL1 or DPLL2 can be configured as an EEC/SEC to output
clocks for the T0 reference point and DPLL3 can be used to output clocks for the T4 reference point.
Clocks generated by DPLL1 or DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The
output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.
Clocks generated by DPLL1 or DPLL2 can be passed through APLL3 which is a voltage controlled crystal oscillator (VCXO) based jitter attenuat-
ing APLL. APLL3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. The output clocks gener-
ated by APLL3 are suitable for serial 40GBASE-R and lower rate interfaces.
The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be con-
nected to either DPLL1 or DPLL3.
All 82P33831 control and status registers are accessed through an I2C slave microprocessor interface. For configuring the DPLLs, APLL1 and
APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset. APLL3 must be configured via the I2C
slave interface.
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Revision 6, March 24, 2016