821024_14 Datasheet, PDF (6/14 Pages) Integrated Device Technology – QUAD NON-PROGRAMMABLE PCM CODEC

821024 DATA SHEET
OPERATING THE IDT821024
The following descriptions about operation applies to all four channels of
the IDT821024.
Power-on Sequence and Master Clock Configuration
To power on the IDT821024 users should follow this sequence:
1. Apply ground;
2. Apply VCC, finish signal connections;
3. Set PDN1-4 pins high, thus all of the 4 channels are powered down;
The master clock (MCLK) frequency of IDT821024 can be configured
as 2.048 MHz, 4.096 MHz or 8.192 MHz. Using the Transmit Frame Sync
(FSX) inputs, the device determines the MCLK frequency and makes the
necessary internal adjustments automatically. The MCLK frequency must
be an integer multiple of the Frame Sync frequency.
Operating Modes
There are two operating modes for each transmit or receive channel:
standby mode (when the channel is powered down) and normal mode (when
the channel is powered on). The mode selection of each channel is done
by its corresponding PDN pin. When PDNn is 1, Channel N is in standby
mode; when PDNn is 0, Channel N is in normal mode.
In standby mode, all circuits are powered down with the analog outputs
placed in high impedance state.
In normal mode, each channel of the IDT821024 is able to transmit and
receive both PCM and analog information. The normal mode is used when
a telephone call is in progress.
Companding Law Selection
An A/μ pin is provided by IDT821024 for the companding law selection.
When this pin is low, μ-law is selected; when the pin is high, A-law is
selected.
QUAD NON-PROGRAMMABLE
6
PCM CODEC
REVISION A 06/25/14