74FCT163373PV Datasheet, PDF (6/7 Pages) Integrated Device Technology – 3.3V CMOS 16-BIT TRANSPARENT LATCH

IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
6v
V CC
Open
VIN
Pulse
Generator
D.U.T.
R^T
VOUT
50pF
CL
500Ω
500Ω
GND
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
6V
GND
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA
INPUT
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
ETC.
tH
tREM
tH
Set-up, Hold, and Release Times
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Propagation Delay
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
tW
HIGH-LOW-HIGH
PULSE
Pulse Width
1.5V
1.5V
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
6V
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
DISABLE
tPLZ
3V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3V
VOL
VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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