74FCT162244T_09 Datasheet, PDF (6/7 Pages) Integrated Device Technology – FAST CMOS 16-BIT BUFFER/LINE DRIVER Reduced system switching noise

IDT54/74FCT162244T/AT/CT/ET
FAST CMOS 16-BIT BUFFER/LINE DRIVER
TEST CIRCUITS AND WAVEFORMS
V CC
7.0V
VIN
Pulse
Generator
D.U.T.
RT
VOUT
50pF
CL
500Ω
500Ω
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuit for All Outputs
DATA
INPUT
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
ETC.
tH
tREM
tH
Set-up, Hold, and Release Times
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Propagation Delay
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
1.5V
1.5V
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
DISABLE
tPLZ
3.5V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
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