SAP5 Datasheet, PDF (58/66 Pages) Integrated Device Technology – AS-Interface Spec. V3.0 Compliant Universal AS-i IC

SAP51 / SAP5S Datasheet
For the circuit shown in Figure 6.2, R1 and C1 form a low-pass-filter for the delay of the output of the SAP5 for
about 20µs. The transistor performs the inversion; the voltage divider R2/R3 shifts the low level in the range of
1.5V to 2.5V. The high level is provided from the pin’s pull-up feature.
Figure 6.2 Safety Mode Application
5.33/
16MHz
1N4001
ASI+
ZMM 39
100nF
ASI-
OSC1
OSC2
LTGP
CDC
LTGN
UOUT
U5R
D2
D3
D0
D1
+24V
+5V
100nF 100nF 10µF
0V
© 2016 Integrated Device Technology, Inc.
58
January 28, 2016