IDT72T51546 Datasheet, PDF (54/64 Pages) Integrated Device Technology – 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits

IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
RADEN
ESTR
REN
RDADD
OE
Qout
WCLK
FSTR
WRADD
WEN
WADEN
Din
Device 0 PAFn
Bus PAFn
Prev.
PAFn
Device 0
PAF
*A*
*B*
tQS
tQH
*C*
*D*
*E*
*F*
*G*
tQS
tQH
tSTS
tSTH
*H*
*I*
tAS
tAH
D0Q31
000 11111
tOLZ
WX
Prev. Q
tSTS
tSTH
tAS
tAH tAS
tAH
D0 quad4
000 xxx11
D0 Q31
tQS
tQH
tAS
tAH
D7 quad 1
111 xxx00
tA
tA
WX +1
Prev. Q
tSKEW3
1
2
tAS
tAH
D6Q2
110 00010
WD-M+1
D0 Q31
3
tENS
tA
WD - M + 2
D0 Q31
tENH
tA
W0
D6 Q2
DXQuad y
DXQuad y
*AA*
HIGH - Z
*BB*
HIGH-Z
tPAFLZ
D0Quad4
tDS
tDH
Word Wy
D0 Q31
tPAF
tDS
tDH
Wy+1
D0 Q31
tDS
tDH
Wy+2
D0 Q31
tPAF
0xxx xxxx
D0Quad4 1xxx xxxx
D0Quad4 0xxx xxxx
D0Quad4 0xxx xxxx
tPAFHZ
D0Quad4 1xxx xxxx
tPAFLZ
HIGH-Z
D0Quad4 0xxx xxxx
tWAF
*CC*
*DD*
*EE*
*FF*
*GG*
5998 drw36
Cycle:
*A* Queue 31 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Quadrant 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B* No read operation.
*BB* Queue 31 of device 0 is selected on the write port.
*C* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*CC* PAFn continues to show status of Quad4 D0.
The PAFn bus is updated with the quadrant selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*D* A new quadrant, Quad 1 of Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*DD* No write operation.
*E* No read operations occur, REN is HIGH.
*EE* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q31.
*F* Queue 2 of Device 6 is selected for read operations.
*FF* Word, Wy+1 is written into D0 Q31.
*G* Word, Wd-m+2 is read out due to FWFT operation.
*GG* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q31.
*H* No read operation.
*I* Word, W0 is read from Q0 of D6, selected on cycle *F*, due to FWFT.
Figure 31. PAFn - Direct Mode, Flag Operation
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