ICS9EPRS525 Datasheet, PDF (5/20 Pages) Integrated Device Technology – 56-pin CK505 for Embedded Intel Systems

ICS9EPRS525
56-pin CK505 for Embedded Systems
Absolute Maximum Ratings - DC Parameters
PARAMETER
Maximum Supply Voltage
Maximum Supply Voltage
SYMBOL
VDDxxx
VDDxxx_IO
CONDITIONS
Supply Voltage
Low-Voltage Differential I/O Supply
MIN
MAX UNITS Notes
4.6
V
7
3.8
V
7
Maximum Input Voltage
V_IH
3.3V Inputs
Minimum Input Voltage
V_IL
Any Input
Storage Temperature
Ts
-
Input ESD protection
ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied, nor guaranteed.}
3 _{Maximum input voltage is not to exceed VDD}
Electrical Characteristics - Input/Supply/Common Output DC Parameters
4.6
GND - 0.5
-65
150
2000
V 4,5,7
V
4,7
°_C
4,7
V
6,7
PARAMETER
Ambient Operating Temp
Supply Voltage
Supply Voltage
SYMBOL
Tambient
VDDxxx
VDDxxx_IO
CONDITIONS
-
Supply Voltage
Low-Voltage Differential I/O Supply
MIN
0
3.135
0.9975
MAX
70
3.465
3.465
UNITS
°C
V
V
Notes
10
Input High Voltage
Input Low Voltage
Low Threshold Input- High Voltage
Low Threshold Input- FSC = '1'
Voltage
Low Threshold Input- FSA,FSB = '1'
Voltage
V_IHSE
V_ILSE
V_{IH_FS_TEST}
V_{IH_FS_FSC}
V_{IH_FS_FSAB}
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
2
V_DD + 0.3 V
3
V_SS - 0.3
0.8
V
3
2 VDD + 0.3 V
8
0.7
1.5
V
8
0.7 VDD+0.3 V
Low Threshold Input-Low Voltage
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
V_{IL_FS}
V_{IL_CFGHI}
V_{IL_CFGMID}
V_{IL_CFGLO}
I_IN
I_INRES
V_OHSE
V_OLSE
I_DDOP3.3
I_DDOPIO
I_DDiAMT3.3
I_DDiAMTIO
I_DDPD3.3
I_DDPDIO
F_i
L_pin
C_IN
C_OUT
C_INX
T_STAB
3.3 V +/-5%
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
V_IN = V_{DD ,} V_IN = GND
Inputs with pull up or pull down resistors
V_IN = V_{DD ,} V_IN = GND
Single-ended outputs, I_OH = -1mA
Single-ended outputs, I_OL = 1 mA
Full Active, C_L = Full load; Idd 3.3V
Full Active, C_L = Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion of PD to 1st
clock
V_SS - 0.3 0.35
V
2.4 VDD+0.3 V
1.3
2
V
V_SS - 0.3
0.9
V
-5
5
uA
-200
200
uA
2.4
V
0.4
V
115
mA
55
mA
36
mA
10
mA
5
mA
0.1
mA
15
MHz
7
nH
1.5
5
pF
6
pF
6
pF
1.8
ms
9, 10
9, 10
9, 10
2
1
1
10
10
Tdrive_CR_off
Tdrive_CR_on
Tdrive_CPU
T_DRCROFF
T_DRCRON
T_DRSRC
Output stop after CR deasserted
Output run after CR asserted
CPU output enable after
PCI_STOP# de-assertion
400
ns
0
us
10
ns
Tfall_SE
Trise_SE
SMBus Voltage
Low-level Output Voltage
Current sinking at V_OLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Maximum SMBus Operating
Frequency
Spread Spectrum Modulation
Frequency
T_FALL
T_RISE
Fall/rise time of all 3.3V control inputs from 20-80%
V_DD
2.7
V_OLSMB
@ I_PULLUP
I_PULLUP
SMB Data Pin
4
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
F_SMBUS
f_SSMOD
Triangular Modulation
30
10
ns
10
ns
5.5
V
0.4
V
mA
1000
ns
300
ns
100
kHz
33
kHz
IDT^TM 56-pin CK505 for Embedded Intel Systems
1614B—01/21/10
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