ICS9EPRS525 Datasheet, PDF (12/20 Pages) Integrated Device Technology – 56-pin CK505 for Embedded Intel Systems

ICS9EPRS525
56-pin CK505 for Embedded Systems
PCI_STOP# Power Management
SMBus OE Bit
Enable
PCI_STOP#
1
0
Disable
X
CPU_STOP# Power Management
SMBus OE Bit
Enable
PCI_STOP#
1
0
Disable
X
Single-ended Clocks
Stoppable
Running
Free running
Running
Low
Low
Low
Differential Clocks
(Except CPU)
Stoppable Free running
Running
Running
CK= High
CK# = Low
Running
CK= Pull down
CK# = Low
Running
CK= Pull down, CK# = Low
Differential Clocks
Stoppable Free running
Running
Running
CK= High
CK# = Low
CK= Pull down
CK# = Low
Low
Running
Running
CR# Power Management
SMBus OE Bit
CR#
Enable
1
0
Disable
X
Differential Clocks
Stoppable Free running
Running
Running
CK= Pull down, CK# = Low
CK = Pull down, CK# = Low
PD# Power Management
Single-ended Clocks
Device State
Latches Open
w/o Latched input w/Latched input
Power Down
Low
Hi-Z
M1
Virtual Power Cycle
to Latches Open
Differential Clocks
(Except CPU1)
CK= Pull down, CK# = Low
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
CK= Pull down, CK# = Low
CPU1
CK= Pull down, CK# = Low
CK= Pull down
CK# = Low
Running
CK= Pull down, CK# = Low
IDT^TM 56-pin CK505 for Embedded Intel Systems
12
1614B—01/21/10