ICS9DB801C Datasheet, PDF (5/19 Pages) Integrated Device Technology – Eight Output Differential Buffer for PCI Express (50-200MHz)

ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
Pin Description for OE_INV = 1
PIN # PIN NAME PIN TYPE
DESCRIPTION
Active low Input for determining SRC output frequency SRC or
1
SRC_DIV#
INPUT SRC/2.
0 = SRC/2, 1= SRC
2
VDD
POWER Power supply, nominal 3.3V
3
GND
POWER Ground pin.
4
SRC_IN
INPUT 0.7 V Differential SRC TRUE input
5
SRC_IN#
INPUT 0.7 V Differential SRC COMPLEMENTARY input
6
OE0#
INPUT
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
7
OE3#
INPUT
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
8
DIF_0
OUTPUT 0.7V differential true clock outputs
9
DIF_0#
OUTPUT 0.7V differential complement clock outputs
10
GND
POWER Ground pin.
11
VDD
POWER Power supply, nominal 3.3V
12
DIF_1
OUTPUT 0.7V differential true clock outputs
13
DIF_1#
OUTPUT 0.7V differential complement clock outputs
14
OE1#
INPUT
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
15
OE2#
INPUT
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
16
DIF_2
OUTPUT 0.7V differential true clock outputs
17
DIF_2#
OUTPUT 0.7V differential complement clock outputs
18
GND
POWER Ground pin.
19
VDD
POWER Power supply, nominal 3.3V
20
DIF_3
OUTPUT 0.7V differential true clock outputs
21
DIF_3#
OUTPUT 0.7V differential complement clock outputs
22
BYPASS#/PLL
INPUT
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23
SCLK
INPUT Clock pin of SMBus circuitry, 5V tolerant.
24
SDATA
I/O Data pin for SMBus circuitry, 5V tolerant.
IDT^TM/ICS^TM Eight Output Differential Buffer for PCI Express (50-200MHz)
5
ICS9DB801C REV C 08/16/07