ICS9DB801C Datasheet, PDF (14/19 Pages) Integrated Device Technology – Eight Output Differential Buffer for PCI Express (50-200MHz)

ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting
off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the
device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#
drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
PWRDWN#
Tstable
<1mS
DIF
DIF#
Tdrive_PwrDwn#
<300uS, >200mV
IDT^TM/ICS^TM Eight Output Differential Buffer for PCI Express (50-200MHz)
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ICS9DB801C REV C 08/16/07