ICS8422002I-01 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER

ICS8422002I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
PRELIMINARY
AC Electrical Characteristics
Table 5A. AC Characteristics, V_DD = V_DDA = 3.3V ± 5%, V_DDO = 1.8V ±0.2V, T_A = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
140
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] = 10
56
tsk(o)
Output Skew; NOTE 1, 2
TBD
156.25MHz, (1.875MHz – 20MHz)
0.44
tjit()
RMS Phase Jitter (Random);
NOTE 3
125MHz, (1.875MHz – 20MHz)
0.48
62.5MHz, (1.875MHz – 20MHz)
0.49
t_R / t_F
Output Rise/Fall Time
20% to 80%
410
odc
Output Duty Cycle
50
Maximum
170
136
68
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V_DDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics, V_DD = V_DDA = 2.5V ± 5%, V_DDO = 1.8V ±0.2V, T_A = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
140
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] = 10
56
tsk(o)
Output Skew; NOTE 1, 2
TBD
156.25MHz, (1.875MHz – 20MHz)
0.41
tjit()
RMS Phase Jitter (Random);
NOTE 3
125MHz, (1.875MHz – 20MHz)
0.49
62.5MHz, (1.875MHz – 20MHz)
0.50
t_R / t_F
Output Rise/Fall Time
20% to 80%
380
odc
Output Duty Cycle
50
Maximum
170
136
68
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V_DDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER
5
ICS8422002AGI-01 REV. C NOVEMBER 1, 2007