ICS670-01 Datasheet, PDF (5/7 Pages) Integrated Circuit Systems – Low Phase Noise Zero Delay Buffer and Multiplier

ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ZDB AND MULTIPLIER
Figure 1. Skew from ICLK to CLK2, with change in load capacitance (VDD = 3.3V)
300
200
100
0
-100
25
-200
-300
-400
50
75
100
125
150
CLK2 Frequency (MHz)
Skew (ps) 20 pF
Skew (ps) 10 pF
Adjusting Input/Output Skew
The data in Figure 1 can be used to adjust individual circuit characteristics and achieve the minimum possible skew
between ICLK and CLK2. With a 125 MHz output, for example, having a total load capacitance of 15 pF will result
in nearly zero skew between ICLK and CLK2. Note that the load
capacitance includes board trace capacitance, input capacitance of the load being driven by the ICS670-01, and
any additional capacitors connected to CLK2.
Figure 2. Phase Noise for 125 MHz output, 25 MHz clock input (VDD = 3.3V)
0
-20
-40
-60
-80
-100
-120
-140
10.E+0
100.E+0
ICS670 Phase noise
1.E+3
10.E+3
offset frequency
100.E+3
1.E+6
10.E+6
IDT® LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
5
ICS670-01 REV L 012315