ICS670-01 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Low Phase Noise Zero Delay Buffer and Multiplier

ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ZDB AND MULTIPLIER
Pin Assignment
VDD
1
VDD
2
VDD
3
CLK2
4
OE2
5
FBCLK
6
OE1
7
FBIN
8
16
GND
15
GND
14
GND
13
S0
12
S1
11
S2
10
S3
9
ICLK
Multiplier Select Table
S3 S2 S1 S0 CLK2 (and FBCLK) Input Range (MHz)
0 0 0 0 Low (Power down entire
-
chip)
0001
Input x1.333
18 - 120
0010
Input x6
5 - 26.67
0011
Input x1.5
16.67 - 107
0100
Input x3.333
7.5 - 48
0101
Input x2.50
10 - 64
0110
Input x4
6 - 40
0111
Input x1
25 - 160
1000
Input x2.333
11 - 69
1001
Input x2.666
10 - 60
1010
Input x12
5 - 13.33
1011
Input x3
8 - 53.33
1100
Input x10
5 - 16
1101
Input x5
6 - 32
1110
Input x8
5 - 20
1111
Input x2
12 - 80
Pin Descriptions
Pin
Number
1-3
4
5
6
7
8
9
10
11
12
13
14 - 16
Pin
Name
VDD
CLK2
OE2
FBCLK
OE1
FBIN
ICLK
S3
S2
S1
S0
GND
Pin
Type
Pin Description
Input Power supply. Connect all pins to the same voltage (either 3.3 V or 5 V). Pins
1 and 2 supply the analog sections of the chip.
Output Clock output from VCO. Output frequency equals the input frequency times
multiplier.
Input Output clock enable 2. Tri-states the clock 2 output when low.
Output Clock output from VCO. Output frequency equals the input frequency times
multiplier.
Input Output clock enable 1. Tri-states the feedback clock output when low.
Input Feedback clock input.
Input Clock input. Connect to a 5 - 210 MHz clock.
Input Multiplier select pin 3. Determines outputs per table above. Internal pull-up.
Input Multiplier select pin 2. Determines outputs per table above. Internal pull-up.
Input Multiplier select pin 1. Determines outputs per table above. Internal pull-up.
Input Multiplier select pin 0. Determines outputs per table above. Internal pull-up.
Power Connect to ground.
IDT® LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
2
ICS670-01 REV L 012315