ICS557-05A Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Quad Differential PCI-Express Clock Source

ICS557-05A
QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE
Output Structures
IREF
=2.3 mA
6*IREF
See Output Termination
R_R 475_W ^{Sections - Pages 3 ~ 5}
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-05A.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
PCIE SSCG
IDT™ / ICS™ QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE
5
ICS557-05A REV H 092407