ICS557-05A Datasheet, PDF (10/12 Pages) Integrated Circuit Systems – Quad Differential PCI-Express Clock Source

ICS557-05A
QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE
PCIE SSCG
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
R_S
R_T
Dimension or Value Unit
0.5 max
inch
0.2 max
inch
0.2 max
inch
33
ohm
49.9
ohm
Differential Routing on a Single PCB
Dimension or Value Unit
L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max inch
Differential Routing to a PCI Express Connector
Dimension or Value Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch
PCI-Express Device Routing
L1
L2
R_S
L4
L4’
L1’
L2’
R_S
R_T R_T
ICS557-03
Output
Clock
L3’ L3
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
t_OR
500 ps
500 ps
t_OF
0.52 V
0.175 V
0.52 V
0.175 V
IDT™ / ICS™ QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE
10
ICS557-05A REV H 092407