ICS548A-03 Datasheet, PDF (5/7 Pages) Integrated Device Technology – LOW SKEW CLOCK INVERTER AND DIVIDER

ICS548A-03
LOW SKEW CLOCK INVERTER AND DIVIDER
CLOCK DIVIDER
AC Electrical Characteristics
VDD = 3.3 V, Ambient Temperature -40 to +85°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency, clock
f_IN
input, PLL on
10
120 MHz
Input Frequency, clock
f_IN
input, PLL off
0
160 MHz
Output Frequency (see
table on page 2)
f_OUT Mode dependent
0
120 MHz
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Output Enable Time, OE
high to output on
t_OR 0.8 to 2.0 V
t_OF 2.0 to 0.8 V
t_DC At VDD/2
0.84
ns
0.74
ns
45
50
55
%
50
ns
Output Disable Time, OE
to tri-state
50
ns
Absolute Clock Period
Jitter. PLL modes
Deviation from mean
150
ps
One Sigma Clock Period
Jitter, PLL modes
60
ps
Output clock skew for
CLK, CLK, or CLK/2
At VDD/2
850 ps
Note 1: The phase relationship between input and output clocks can change at power up. Use the ICS570 or
ICS527 Zero Delay Buffers for a guaranteed phase relationship.
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θ_JA Still air
θ_JA 1 m/s air flow
θ_JA 3 m/s air flow
Thermal Resistance Junction to Case θ_JC
Min.
Typ.
120
115
105
58
Max.
Units
°C/W
°C/W
°C/W
°C/W
IDT™ / ICS™ LOW SKEW CLOCK INVERTER AND DIVIDER
5
ICS548A-03 REV C 063006