89HPES3T3 Datasheet, PDF (5/23 Pages) Integrated Device Technology – 3-Lane 3-Port PCI Express Switch

IDT 89HPES3T3 Data Sheet
Signal
RSTHALT
SWMODE[2:0]
WAKEN
Type
Name/Description
I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES3T3 executes the reset procedure and remains in a reset
state with the Master SMBus active. This allows software to read and write
registers internal to the device before normal device operation begins. The
device exits the reset state when the RSTHALT bit is cleared in the
PA_SWCTL register by the SMBus master.
I Switch Mode. These configuration pins determine the PES3T3 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
I/O Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through WAKEDIR bit setting in
the WAKEUPCNTL register.
Table 4 System Pins (Part 2 of 2)
Signal
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
Type
Name/Description
I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 5 Test Pins
Signal
V_DDCORE
V_DDI/O
V_DDPE
V_DDAPE
V_TTPE
V_SS
Type
Name/Description
I Core VDD. Power supply for core logic.
I I/O VDD. LVTTL I/O buffer power supply.
I PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
I PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
I PCI Express Termination Power.
I Ground.
Table 6 Power and Ground Pins
5 of 23
September 7, 2007