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89HPES3T3 Datasheet, PDF (1/23 Pages) Integrated Device Technology – 3-Lane 3-Port PCI Express Switch | |||
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3-Lane 3-Port
PCI Express® Switch
®
89HPES3T3
Data Sheet
Advance Information*
Device Overview
The 89HPES3T3 is a member of IDTâs PRECISE⢠family of PCI
Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
Features
â High Performance PCI Express Switch
â Three 2.5Gbps PCI Express lanes
â Three switch ports
â x1 Upstream port
â Two x1 Downstream ports
â Low latency cut-through switch architecture
â Support for Max payload sizes up to 256 bytes
â One virtual channel
â Eight traffic classes
â PCI Express Base Specification Revision 1.1 compliant
â Flexible Architecture with Numerous Configuration Options
â Automatic lane reversal on all ports
â Automatic polarity inversion on all lanes
â Ability to load device configuration from serial EEPROM
â Legacy Support
â PCI compatible INTx emulation
â Bus locking
â Highly Integrated Solution
â Requires no external components
â Incorporates on-chip internal memory for packet buffering and
queueing
â Integrates three 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
â Reliability, Availability, and Serviceability (RAS) Features
â Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
â Supports ECRC and Advanced Error Reporting
â Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
â Compatible with Hot-Plug I/O expanders used on PC mother-
boards
â Power Management
â Utilizes advanced low-power design techniques to achieve low
typical power consumption
â Supports PCI Power Management Interface specification (PCI-
PM 1.2)
â Unused SerDes are disabled.
â Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
â Testability and Debug Features
â Built in Pseudo-Random Bit Stream (PRBS) generator
â Numerous SerDes test modes
â Ability to bypass link training and force any link into any mode
â Provides statistics and performance counters
Block Diagram
Frame Buffer
3-Port Switch Core / 3 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 0)
(Port 2)
(Port 3)
© 2007 Integrated Device Technology, Inc.
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 23
*Notice: The information in this document is subject to change without notice
September 7, 2007
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