8421002I-01 Datasheet, PDF (5/15 Pages) Integrated Device Technology – FemtoClock Crystal-to-HSTL Frequency Synthesizer

8421002I-01 DATA SHEET
TABLE 5A. AC CHARACTERISTICS, V = V = 3.3V±5%,V = 1.8V±0.2V, TA = -40°C TO 85°C
DD
DDA
DDO
Symbol Parameter
f
OUT
tsk(o)
tjit(Ø)
t /t
RF
odc
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz,(1.875MHz - 20MHz)
20% to 80%
Minimum
140
112
56
215
48
Typical
0.44
0.48
0.49
Maximum Units
170
MHz
136
MHz
68
MHz
20
ps
ps
ps
ps
815
ps
52
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V /2.
DDO
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, V = V = 2.5V±5%,V = 1.8V±0.2V, TA = -40°C TO 85°C
DD
DDA
DDO
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
140
f
Output Frequency
OUT
F_SEL[1:0] = 01
112
F_SEL[1:0] = 10
56
tsk(o) Output Skew; NOTE 1, 3
156.25MHz, (1.875MHz - 20MHz)
0.41
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
125MHz, (1.875MHz - 20MHz)
0.49
62.5MHz,(1.875MHz - 20MHz)
0.50
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
315
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V /2.
DDO
NOTE 2 Please refer to the Phase Noise Plot.
NOTE 3 This parameter is defined in accordance with JEDEC Standard 65.
Maximum Units
170
MHz
136
MHz
68
MHz
20
ps
ps
ps
ps
715
ps
52
%
REVISION B 8/14/15
5
FEMTOCLOCKS™ CRYSTAL-TO-HSTL
FREQUENCY SYNTHESIZER