71024S15YI Datasheet, PDF (5/8 Pages) Integrated Device Technology – CMOS Static RAM 1 Meg (128K x 8-Bit)

IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Timing Waveform of Read Cycle No. 1⁽¹⁾
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2^(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OEis LOW.
5. Transition is measured ±200mV from steady state.
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