8V97053 Datasheet, PDF (49/58 Pages) Integrated Device Technology – Low Power Wideband Fractional RF Synthesizer / PLL

8V97053 Datasheet
Schematic Example
Figure 13A and Figure 13B show general application schematic
examples for the 8V97053.
For power rails, bypass capacitors must be provided to all power
supply pins. Suggest at least one bypass capacitor per power pin.
Value can be ranged from 0.01uF or 0.1uF. Mix values of bypass
capacitor can help filtering wider range of power supply noise.
The 8V97053 input is high impedance. The input termination
depends on the driver type termination requirements. In these
examples, the 8V97053 REF_IN input is terminated with a matched
load termination. For transmission line with characteristic impedance
Zo = 50, the termination resistor R8 is 50. The input is self biased
to proper DC offset after the AC coupling.
The loop filter values can be calculated to meet the loop bandwidth
requirement. Please refer to the section, "Loop Filter Calculations" for
detailed calculations. For fast lock mode, the loop filter can be
configured as Fast Lock Loop Filter Option 1 or Fast Lock Loop Filter
Option 2 shown in Figure 13A.
Fast Lock Loop Filter Option 1 is Parallel Resistor Configuration. For
normal operating mode, only R5 is active and R5 = Rs, where Rs is
the resistor value for normal operating mode loop bandwidth. In fast
lock mode, the combination of R4 in parallel with R5 is active. For
example, in normal operation mode, if the charge pump current is set
at 0000 (ICP = 310uA), then, in fast lock mode, the loop bandwidth is
set larger by increasing the charge pump current to ICP~5mA (ICP
setting = 1111 or 16 times the normal charge pump current). The
combination of the R4 and R5 in parallel is 1/4 * Rs.
Fast Lock Loop Filter Option 2 is Series Resistor Configuration. 
For normal operating mode, both R6 and R7 are active and 
R6 + R7 = Rs. For fast lock mode, only R6 is active. For example, in
normal operation mode, if the charge pump current is set at 0000
(ICP = 310uA), then, in fast lock mode, the loop bandwidth is set
larger by increasing the charge pump current to ICP~5mA (ICP
setting = 1111 or 16 times the normal charge pump current). 
The sum of R6 and R7 equals to Rs, i.e. R6 + R7 = Rs. 
R6 = 1/4 * Rs and R7 = 3/4 * Rs.
The 8V97053 output pull-up loading can be resistors or inductors.
The pull up resistor value is typically 50. Resistor pull up loading
covers wide range of output frequencies. For inductor pull up loading,
the inductor value is frequency dependent. One inductor value
cannot cover all the output frequency range. This example shows the
L = 3.9nF that is suitable for approximately 2GHz operating
frequency. The output can also drive single ended LO input. Figure
13B shows an example of the 8V97053 output driving single ended
LO input of the mixer through an LC balun. The LC balun component
values are frequency dependent. These values can be adjusted to
optimize the performance. Single ended LO receiver input also can
tap to one side of the differential driver using resistor loading or
inductor loading. For single ended LO input, both sides of the
differential driver still need to be loaded with pull up. The output
power level can also be adjusted further through programming.
©2016 Integrated Device Technology, Inc.
49
September 22, 2016