8V97053 Datasheet, PDF (13/58 Pages) Integrated Device Technology – Low Power Wideband Fractional RF Synthesizer / PLL

8V97053 Datasheet
Band Selection Disable
For a given frequency, the output phase can be adjusted when using
the Band_Sel_Disable bit (Bit D28 in Register 1). When this bit is
enabled (Bit D28 set to 1), the part does not do a VCO band selection
or phase resync after an update to Register 0.
When the Band_Sel_Disable bit is set to 0, and when Register 0 is
updated, the part proceeds to a VCO band selection, and to a phase
resync if phase_resync is also enabled in Register 3 (Bits[D16:D15]
set to D16 = 1 and D15 = 0).
The “Band_Sel_Disable” bit is useful when the user wants to make
small changes in the output frequency (<1MHz from the nominal
frequency) without recalibrating the VCO and minimizing the settling
time.
Phase Adjust
The output phase is controlled by the 12-Bit phase value
Bits[D26:D15] in Register 1. The output phase can vary over 360°
with a 360°/MOD step. For dynamic adjustments of the phase after
an initial phase setting, it is recommended to select the
BAND_SEL_DISABLE function by setting the Band_Sel_Disable bit
(D28 in Register 1) to 1.
The PHASE value can be extended to 16-bits when using the
extended registers. In this 16 bit mode, both registers 1 and 7 define
the PHASE value.
Phase Resync
The phase alignment function operates based on adjusting the
“fractional” phase, so the phase can settle to any one of the MOD
phase offsets, MOD being the modulus of the fractional feedback
divider.
The phase adjustment can provide a 0-360° of phase adjust,
assuming that the output divider ratio is set to 1.
The phase step is TVCO/MOD for the normal case of fundamental
feedback. TVCO is the period of the VCO.
The feedback select bit (FbkSel bit, Bit D23 in Register 4) gives the
choices of fundamental feedback or divided feedback. This bit
controls the mux that sends the VCO signal or the output divider
signal to the feedback loop. The user can get larger phase steps in
the divided mode, but the phase noise may be degraded, especially
in fractional mode. Should the user select this option, the phase
adjustment step would be ~T_OUT/MOD, where T_OUT is the output
signal period.
When the part is in fractional mode, the device is dithering the
feedback divider value. As an example, when using a 4GHz VCO
frequency, the feedback divider value may dither between Div-by-20
and Div-by-21. Since the period is 250ps, there will be 250ps of jitter
added to the phase detector. This jitter is filtered by the loop, but can
still show up at the output if the loop bandwidth is high. When using
a divider before the feedback divider, the effective VCO period is
increased. If a Div-by-64 is used for example, the period becomes
64x250ps = 16ns. This means that there could be an additional 16ns
of jitter at the PFD, rather than 250ps. It is more challenging for the
loop to filter this larger amount of jitter and this will degrade the
overall performance of the part, unless the user chooses to use a
very low loop bandwidth. With normal loop bandwidth configurations
(for optimal noise), the phase noise would be degraded when using
a divided feedback mode.
The Phase Resync is controlled by setting Bits[D16:D15] in Register
3 to D16 = 1 and D15 = 0. When phase resync is used, an internal
timer generates sync signals every T_SYNC where:
T_SYNC = ClkDiv x MOD x T_PFD
(5)
ClkDiv = the value (from 1 and 4095) programmed in the 12-bit
clock counter in Bits[D14:D3] in Register 3. The 12-bit
counter is used as a timer for Fast Lock and for the Phase
Resync function.
MOD = the Modulus value (Bits[D14:D3] of Register 1)
T_PFD = the PFD period
In Equation 5, the minimum of either MOD value or 4095 is used for
calculating T_SYNC when in 16-bit mode.
Figure 7. 12-bit Counter for Fast Lock and Phase Resync
After the user program a frequency, the second sync pulse coming
from the 12-bit counter, after the nCS is asserted high, is used to
resynchronize the output phase to the input phase. To ensure that the
PLL is locked before to resynchronize the output phase, TSYNC
must be larger than the worst case lock time.
©2016 Integrated Device Technology, Inc.
13
September 22, 2016