IDT82V3355 Datasheet, PDF (46/135 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL

IDT82V3355
5
JTAG
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
dard except the following:
• The output boundary scan cells do not capture data from the
core and the device does not support EXTEST instruction;
• The TRST pin is set low by default and JTAG is disabled in order
to be consistent with other manufacturers.
The JTAG interface timing diagram is shown in Figure 17.
t_TCK
SYNCHRONOUS ETHERNET WAN PLL
TCK
t_S
t_H
TMS
TDI
t_D
TDO
Figure 17. JTAG Interface Timing Diagram
Table 34: JTAG Timing Characteristics
Symbol
t_TCK
t_S
t_H
t_D
Parameter
TCK period
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
Min
Typ
Max
Unit
100
ns
25
ns
25
ns
50
ns
JTAG
46
May 19, 2009