IDT82V3355 Datasheet, PDF (23/135 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL

IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
3.6.2 FORCED SELECTION
In Forced selection, the selected input clock is set by the
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni-
toring) do not affect the input clock selection.
3.6.3 AUTOMATIC SELECTION
In Automatic selection, the input clock selection is determined by its
validity and priority. The validity depends on the results of input clock
quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring).
In all the qualified input clocks, the one with the highest priority is
selected. The priority is configured by the corresponding
INn_CMOS_SEL_PRIORITY[3:0] bits (n = 1, 2 or 3) / the
INn_DIFF_SEL_PRIORITY[3:0] bits (n = 1 or 2). If more than one quali-
fied input clock is available and has the same priority, the input clock
with the smallest ‘n’ is selected. See Table 9 for the ‘n’ assigned to the
input clock.
Table 9: ‘n’ Assigned to the Input Clock
Input Clock
IN1_CMOS
IN1_DIFF
IN2_CMOS
IN2_DIFF
IN3_CMOS
‘n’ Assigned to the Input Clock
1
2
3
4
5
Table 10: Related Bit / Register in Chapter 3.6
Bit
Register
EXT_SW
T0_INPUT_SEL[3:0]
T4_LOCK_T0
T0_FOR_T4
T4_INPUT_SEL[3:0]
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
T4_T0_SEL
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
T4_INPUT_SEL_CNFG
IN1_IN2_CMOS_SEL_PRIORITY_CNFG,
IN3_CMOS_SEL_PRIORITY_CNFG
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
T4_T0_REG_SEL_CNFG
Note: * The setting in the 27, 28 and 2A registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Address (Hex)
0B
50
51
27 *, 2A *
28 *
07
Functional Description
23
May 19, 2009