8V49NS0312 Datasheet, PDF (46/57 Pages) Integrated Device Technology – FemtoClock NG Clock Generator with 4 Dividers

8V49NS0312 Datasheet
Schematic Layout
Figure 19 shows an example 8V49NS0312 application schematic operating the device at V_CC = 3.3V. This example focuses on functional
connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control
inputs are properly set for the application.
To demonstrate the range of output stage configurations possible, the application schematic assumes that the 8V49NS0312 is programmed
over I²C. For alternative DC coupled LVPECL options please see IDT Application Note, AN-828; for AC coupling options use IDT Application
Note, AN-844.
For a 12pF parallel resonant crystal, tuning capacitors C145 and C146 are recommended for frequency accuracy. Depending on the parasitic
of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load
capacitance specifications can be used. This will require adjusting C145 and C146. For this device, the crystal tuning capacitors are required
for proper operation.
Crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board.
Capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise
coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. Routing I²C under
the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the crystal oscillation. In
fact, I²C transition times are short enough to capacitively couple into the crystal-oscillator loop if they are routed close enough to the crystal
traces.
In layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the OSCI and OSCO pins, traces to the crystal
pads, the crystal pads and the tuning capacitors. Using a crystal on the top layer as an example, void all signal and power layers under the
crystal connections between the top layer and the ground plane used by the 8V49NS0312. Then calculate the parasitic capacity to the ground
and determine if it is large enough to preclude tuning the oscillator. If the coupling is excessive, particularly if the first layer under the crystal is
a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. The ground connection
of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to connect the tuning
cap ground to the ground plane as close to the 8V49NS0312 as possible as shown in the schematic.
As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power
supply isolation is required. The 8V49NS0312 provides separate power supplies to isolate any high switching noise from coupling into the
internal PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB
as close to the power pins as possible. The ferrite bead and the 0.1uF capacitor in each power pin filter should always be placed on the device
side of the board. The other components can be on the opposite side of the PCB if space on the top side is limited. Pull up and pull down
resistors to set configuration pins can all be placed on the PCB side opposite the device side to free up device side area if necessary.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. Depending
on the application, the filter may need to be adjusted to get a lower cutoff frequency to adequately attenuate low-frequency noise. Additionally,
good general design practices for power plane voltage stability suggest adding bulk capacitance in the local area of all devices.
For additional layout recommendations and guidelines, contact [e-mail].
©2016 Integrated Device Technology, Inc.
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September 2, 2016