8V49NS0312 Datasheet, PDF(25/57 Page) Integrated Device Technology – FemtoClock NG Clock Generator with 4 Dividers

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8V49NS0312 Datasheet, PDF (25/57 Pages) Integrated Device Technology – FemtoClock NG Clock Generator with 4 Dividers

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8V49NS0312 Datasheet

Table 19: Device Control Register Bit Field Locations and Descriptions

Device Control Register Block Field Locations

Address (Hex)

INIT_CLK

RELOCK

PB_CAL

Rsvd

EN_A

EN_B

EN_C

EN_D

Device Control Register Block Field Descriptions

Bit Field Name

INIT_CLK

RELOCK

Field Type

W/Oa

Default Value

Description

Writing a â1â to this bit location will cause output dividers to be synchronized. Must be

done every time a divider value is changed if output divider synchronization is desired.

This bit will auto-clear after output divider synchronization is completed.

Writing a â1â to this bit location will cause the PLL to re-lock. This bit will auto-clear.

PB_CAL

W/Oa

Precision Bias Calibration:

Setting this bit to 1 will start the calibration of an internal precision bias current source.

The bias current is used as reference for outputs configured as LVDS and for as

reference for the charge pump currents. This bit will auto-clear after the calibration is

completed.

EN_A

EN_B

EN_C

Output Enable control for Bank A:

R/W

0 = Bank A outputs QA[0:3] disabled to logic-low state (QAx = 0, nQAx = 1)

1 = Bank A outputs QA[0:3] enabled

Output Enable control for Bank B:

R/W

0 = Bank B outputs QB[0:3] disabled to logic-low state (QBx = 0, nQBx = 1)

1 = Bank B outputs QB[0:3] enabled

Output Enable control for Bank C:

R/W

0 = Bank C outputs QC[0:1] disabled to logic-low state (QCx = 0, nQCx = 1)

1 = Bank C outputs QC[0:1] enabled

EN_D

Output Enable control for Bank D:

0 = Bank D outputs QD[0:1] disabled to logic-low state (QD0 = 0, nQD0 = 1, QD1 = 0)

R/W

Note that if Bank D is powered down via the PD_D bit or the QD1 output is powered

down by the PD_QD1 bit, then QD1 will be in High-Impedance regardless of the state

of this bit.

1 = Bank D outputs QD[0:1] enabled

Rsvd

R/W

Reserved. Always write 0 to this bit location. Read values are not defined.

a. These bits are read as â0â. When a â1â is written to them, it will have the indicated effect and then self-clear back to â0â.

September 2, 2016

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