IDT72T36135M_16 Datasheet, PDF (42/48 Pages) Integrated Device Technology – 2.5V 18M-BIT HIGH-SPEED TeraSync

IDT72T36135M 2.5V 18M-BIT TeraSync™ 36-BIT FIFO
524,288 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
tCLKH
tCLKL
WEN
tENS
tENH
PAF[1:2]
RCLK
D - (m + 1) words in FIFO
tPAFA
D - m words
in FIFO
tPAFA
D - (m + 1) words
in FIFO
tENS
REN
NOTES:
1. m = PAF[1:2] offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 524,288 for the IDT72T36135M.
In FWFT Mode: D = 524,289 for the IDT72T36135M.
3. PAF[1:2] is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS = LOW.
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Figure 24. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
tCLKH
tCLKL
tENS
tENH
PAE[1:2]
RCLK
REN
n words in FIFO⁽²⁾,
n + 1 words in FIFO⁽³⁾
tPAEA
n + 1 words in FIFO⁽²⁾,
n + 2 words in FIFO⁽³⁾
tPAE
A
tENS
NOTES:
1. n = PAE[1:2] offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE[1:2] is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
n words in FIFO⁽²⁾,
n + 1 words in FIFO⁽³⁾
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Figure 25. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
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