IDT72T36135M_16 Datasheet, PDF (1/48 Pages) Integrated Device Technology – 2.5V 18M-BIT HIGH-SPEED TeraSync

2.5V 18M-BIT HIGH-SPEED TeraSync^TM
FIFO 36-BIT CONFIGURATIONS
524,288 x 36
IDT72T36135M
FEATURES:
• Industry’s largest FIFO memory organization:
IDT72T36135 ⎯ 524,288 x 36 - 18M-bits
• Up to 200 MHz Operation of Clocks
• Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync
devices
• User selectable HSTL/LVTTL Input and/or Output
• User selectable Asynchronous read and/or write port timing
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input disables Write Port
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Separate SCLK input for Serial programming of flag offsets
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty and Full flags signal FIFO status
• Select IDT Standard timing (using EF[1:2] and FF[1:2] flags) or First
Word Fall Through timing (using OR[1:2] and IR[1:2] flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
50% more space saving than the leading 9M-bit FIFOs
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
WEN _WCLK/WR
WCS
D0 -Dn (x36)
INPUT REGISTER
ASYW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
Vref
WHSTL
RHSTL
SHSTL
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
JTAG CONTROL
(BOUNDARY
SCAN)
HSTL I/0
CONTROL
RAM ARRAY
524,288 x 36
OUTPUT REGISTER
OE
Q0 -Qn (x36)
LD SEN SCLK
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR[1:2]
PAF[1:2]
EF/OR[1:2]
PAE[1:2]
FWFT/SI
PFM
FSEL0
FSEL1
READ
CONTROL
LOGIC
RT
MARK
ASYR
RCLK/RD
REN
RCS
6723 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2016
DSC-6723/5