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ICS1894-32_10 Datasheet, PDF (42/50 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE | |||
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M MII Media Independent Interface: Receive Latency
The table below lists the significant time periods for the 100M MII/100M Stream Interface receive latency. The time
periods consist of timings of signals on the following pins:
⢠TP_RX (that is, TP_RXP and TP_RXN)
⢠RXCLK
⢠RXD (that is, RXD[3:0])
The 100M MII/100M Stream Interface: Receive Latency Timing Diagram shows the timing diagram for the time
periods.
Time
Period
Parameter
t1 First Bit of /J/ into TP_RX to /J/ on RXD
Conditions
100M MII
Min. Typ. Max. Units
â 16 17 Bit times
100M MII/100M Stream Interface: Receive Latency Timing Diagram
TP_RXâ
RXCLK
RXD
t1
â Shown
unscrambled.
Reset: Power-On Reset
The table below lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
⢠VDD
⢠TXCLK
The Power-On Reset Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter
t1 VDD ⥠2.7 V to Reset Complete
Conditions Min. Typ. Max. Units
â
40 45 500 ms
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
42
ICS1894-32 REV K 060110
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