ICS1894-32_10 Datasheet, PDF (16/50 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Register Map
Register Address
0
1
2,3
4
5
6
7
8
9 through 15
16 through 31
Register Name
Control
Status
PHY Identifier
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next Page Transmit
Auto-Negotiation Next Page Link Partner Ability
Reserved by IEEE
Vendor-Specific (IDT) Registers
Basic / Extended
Basic
Basic
Extended
Extended
Extended
Extended
Extended
Extended
Extended
Extended
PHYCEIVER
Register Description
Bit
Definition
When Bit = 0
When Bit = 1
Access ² SF² Default³ Hex
Register 0h - Control
0.15
Reset
No effect
Reset mode
RW SC
0
3
0.14
Loopback enable
0.13
Speed select¹
Disable Loopback mode Enable Loopback mode
RW
–
0
10 Mbps operation
100 Mbps operation
RW
–
1
0.12
Auto-Negotiation enable Disable Auto-Negotiation Enable Auto-Negotiation
RW
–
1
0.11
Low-power mode
Normal power mode
Low-power mode
RW
–
0
0/5‡
0.10
Isolate
No effect
Isolate from MII
RW
–
0/1‡
0.9
Auto-Negotiation restart No effect
Restart Auto-Negotiation
RW SC
0
0.8
Duplex mode¹
Half-duplex operation
mode not supported
Full-duplex operation
RW
–
1
0.7
—
—
—
RW
–
0
0
0.6
IEEE reserved
Always 0
N/A
RO
–
0†
0.5
IEEE reserved
Always 0
N/A
RO
–
0†
0.4
IEEE reserved
Always 0
N/A
RO
–
0†
0.3
IEEE reserved
Always 0
N/A
RO
–
0†
0
0.2
IEEE reserved
Always 0
N/A
RO
–
0†
0.1
IEEE reserved
Always 0
N/A
RO
–
0†
0.0
IEEE reserved
Always 0
N/A
RO
–
0†
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
16
ICS1894-32 REV K 060110