ADC1443D125HD-C1 Datasheet, PDF (42/50 Pages) Integrated Device Technology – Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B-compliant CGVxpress serial outputs

Integrated Device Technology
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Table 43. JESD204B_CTRL2register (address 0811h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
DCS_periodic_rst
R/W
0
defines the LMFC modes
0;DCS reset is done once
1; DCS reset is donce at each SYSREF or SYNC
6
DCS_periodic_rst
R/W
0
enables the LMFC reset
0;DCS reset is disabled
1; DCS reset is enabled
5 to 0 -
-
00000
reserved
Table 44. JESD204B_CTRL3 register (address 0812h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 4 -
-
0000
reserved
3
sync_at_lmfc_en
R/W
0
define the relation between the SYNC and the LMFC
0;SYNC is fetched directely (JESD204A mode)
1; SYNC is taken at next LMFC boundary (
Subclass 1 and Subclass 2)
2
-
-
0
reserved
1
sync_capture_path
R/W
0
SYNC mode
0;JESD204A mode
1; Subclass 1 and Subclass 2
0
-
-
0
reserved
Table 45. IP_DEBUG_OUT1 register (address 0816h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 2 -
-
000000
not used
1 to 0 PATTERN_OUT[9:8]
R/W
10
2 most significant bits of output stage debug word
(inserted just before serializer)
Table 46. IP_DEBUG_OUT2 register (address 0817h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0 PATTERN_OUT[7:0]
R/W
1010 1010 8 least significant bits of output stage debug word
(inserted just before serializer)
Table 47. IP_DEBUG_IN1 register (address 0818h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0 PATTERN_IN[15:8]
R/W
1010 1010 8 most significant bits of input stage debug word
(inserted in place of ADC data)
ADC1443D_SER
Data sheet
Rev. 3.4 — 10 October 2012
© IDT 2012. All rights reserved.
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