ADC1443D125HD-C1 Datasheet, PDF (35/50 Pages) Integrated Device Technology – Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B-compliant CGVxpress serial outputs

Integrated Device Technology
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
11.5.3 Detailed register description
The tables in this section contain detailed descriptions of the registers.
11.5.3.1 ADC control registers
Table 20. CHIP_RESET register (address 0000h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0 SW_RST
R/W
-
resets global and local registers for any value “1”
written at any bit (autoclear).
Table 21. CHIP_RESET register (address 0005h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
resets global and local registers
0
no reset
1
performs a reset to the default values (autoclear)
6 to 0 -
-
-
not used
Table 22. OP_MODE register (address 0006h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
7 to 2 -
-
-
1 to 0 OP_MODE[1:0]^[1]
R/W
00
01
10
11
[1] Local register.
Description
not used
operating mode for the selected channel
normal (power-up)
power-down
sleep
not used
Table 23. CLK_CFG register (address 0007h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
7 to 5 -
-
-
4
SE_SEL
R/W
0
1
3
DIFF_SE
R/W
0
1
Description
not used
single-ended clock input pin selection
CLKP
CLKM
differential/single-ended clock input selection
fully differential
single-ended
ADC1443D_SER
Data sheet
Rev. 3.4 — 10 October 2012
© IDT 2012. All rights reserved.
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